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12-bit, sdtv/hdtv 3d comb filter, video decoder, and graphics digitizer data sheet ADV7802 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features 4 noise shaped video (nsv) 12-bit adcs true 12-bit high dynamic range processing 12-channel analog input mux 36-bit digital ycrcb/rgb output 12-bit deep color processing analog monitor output ntsc/pal/secam color standards support ntsc/pal 3d comb filter 3d digital noise reduction (dnr) advanced time-base correction (tbc) with frame synchronization interlaced-to-progressive conversion for 525i and 625i advanced vbi data slicer, including teletext, cc, and v-chip if compensation filter scart fast blank support including slow switch detect programmable internal antialias filters weak, poor time-base, and nonstandard signal support vertical peaking, horizontal peaking, cti, lti simultaneous interlaced and progressive parallel output for 525i/525p and 625i/625p 525p/625p component progressive scan support 720p/1080i/1080p component hdtv support digitizes rgb graphics with maximum pixel clock rate of 135 mhz (ADV7802bstz-150 model only) 24-bit digital input port supports data from dvi/hdmi rx ic any-to-any, advanced 3 3 color space conversion matrix flexible output pixel interface supporting 8-/10-/12-/16-/ 20-/24-/30-/36-bit sdr/ddr 4:2:2/4:4:4 data formats programmable interrupt request output pin applications av receivers lcd hdtvs pdp hdtvs crt hdtvs hdtv stbs with pvr dvd recorders with progressive scan input support projectors gr rgb scart input mux mux clamp clamp clamp clamp adc adc adc adc analog input interface dac yprpb s-video adc_clk digital input interface sync pll sdp cp dig ana sdp cp dac hs_in1 vs_in1 sog xtal analog digital adc, core, memory clk generation dds for sdp line-locked clk generation standard definition processor (sdp) ddr/sdr sdram interface core_clk ddr/sdr sdram interface clk data (16) address (14) control (9) vbi data processor (vdp) component processor (cp) core_clk output formatting ADV7802 i 2 c configuration y cb cr hs vs fld de llc cvbs 12 12 12 06654-001 figure 1. ADV7802 block diagram general description the ADV7802 1 is a high quality, single-chip, multiformat 3d comb filter, video decoder, and graphics digitizer. this multiformat 3d comb filter decoder supports the conversion of pal, ntsc, and secam standards in the form of a composite or an s-video into a digital itu-r bt.656 format. the ADV7802 also supports the decoding of a component rgb/yprpb video signal into a digital ycrcb or rgb pixel output stream. the support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hd and smpte standards. graphics digitization is supported by the ADV7802; it is capable of digitizing rgb graphics signals from vga to sxga rates and converting them into a digital rgb or ycrcb pixel output stream. scart and overlay functionality are enabled by the ability of the ADV7802 to simultaneously process cvbs and standard definition rgb signals. the ADV7802 contains two main processing sections. the first section is the standard definition processor (sdp), which processes all pal, ntsc, secam, and component (up to 525p/625p) signal types. the second section is the component processor (cp), which processes yprpb and rgb component formats, including rgb graphics. 1 protected by u.s. patent number 4,907,093 and other intellectual property rights.
ADV7802 data sheet rev. d | page 2 of 36 table of contents features .............................................................................................. 1 ap plications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 v ideo specifications ..................................................................... 6 timing characteristics ................................................................ 7 timing diagrams .......................................................................... 8 analog specifications ................................................................... 9 absolute maximum ratings .......................................................... 10 package thermal performance ................................................. 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 theory of operation ...................................................................... 14 key features ................................................................................ 14 analog front end ....................................................................... 14 standard definition processor ................................................. 14 vbi data processor .................................................................... 15 component processor ............................................................... 15 additional features .................................................................... 16 single data rate (sdr) .............................................................. 16 double data rate (ddr) .......................................................... 16 recommended external loop filter components .................... 17 typical connection diagrams ...................................................... 18 pixel input/output formatting .................................................... 21 pixel data output modes highlights ...................................... 21 digital video input port highlights ........................................ 21 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 8/ 11 revision d : initial version
data sheet ADV7802 rev. d | page 3 of 36 functional block diagram 12 12 12 12 2d comb 3d comb tbc 525p/625p support macrovision detection standard autodection cti lti vertical peaking horizontal peaking fastblank overlay control mux clamp clamp clamp clamp antialias filter antialias filter antialias filter antialias filter input mux adc adc adc adc 12 12 12 12 12 ain1 to ain12 cvbs s-video yprpb scart - (cbvs + rgb) g raphics rgb fb cvbs out ddr/sdr-sdram interface standard definition processor (sdp) i to p colorspace conversion av code insertion digital fine clamp gain control offset control av code insertion macrovision detection active peak and agc digital input port dvi or hdmi serial interface control and vbi data vbi data processor (vdp) colorspace conversion funct1 core clk dac 24 sync processing and clock generation sspd stdi hs_in2 p30 to p53 vs_in2 clkin de_in hs_in1 vs_in1 sclk1 sclk2 sda2 sda1 alsb sog soy 54 pixel data p0 to p53 output fifo and formatter cs/hs_out vs_out fld_de_out sfl/sync_out llc int ADV7802 component processor (cp) 06654-002 figure 2.
ADV7802 data sheet rev. d | page 4 of 36 specifications electrical character istics av d d = 3.15 v to 3.45 v, dvdd = 1.75 v to 1.85 v, dvddio = 3.0 v to 3.6 v, dvddio_sdram = 2.35 v to 2.6 5 v (ddr), dvddio_sdra m = 3.2 v to 3.4 v (sdr), pvdd = 1. 71 v to 1.89 v, nominal input range 1.6 v. t a = 0c to 85c, unless otherwise noted . table 1 . parameter 1 symbol test conditions min typ max unit static performance 2 , 3 resolution ( e ach adc) n 12 bits integral nonlinea rity 4 inl bsl at 27 mhz (at a 12 - bit level) ? 1.0/+1.5 lsb bsl at 54 mhz (at a 12 - bit level) ? 1.5/+2.0 lsb bsl at 74 mhz (at a n 11- bit level) ? 1.4/+1.2 lsb bsl at 110 mhz (at a 10 - bit level) ?0.8/+2.0 lsb bsl at 150 mhz (at a n 8- bit lev el) ?2.0/+2.0 lsb differential nonlinearity 4 dnl at 27 mhz (at a 12 - bit level) ? 0.6/+0.7 lsb at 54 mhz (at a 12 - bit level) ? 0.6/+0.8 lsb at 74 mhz (at a n 11- bit level) ? 0.9/+0.75 lsb at 110 mhz (at a 10 - bit level) ?0.5/+1.0 lsb at 150 mhz (at an 8 - bit level) ?0.7/+1.5 lsb power requirements 5 digital core power supply dvdd 1.75 1.8 1.85 v digital i/o power supply dvddio 3.0 3.3 3.6 v pll power supply pvdd 1.71 1.8 1.89 v analog power s upply avdd 3.15 3.3 3.45 v memory interface power supply dvddio_sdram ddr 2.35 2.5 2.65 v sdr 3.2 3.3 3.4 v digital core supply current i dvdd cvbs input sampling at 54 mhz 236 ma graphics rgb sampling at 78 mhz 103 ma scart rgb fb sampling at 54 mhz 236 ma 525p input sampling at 54 mhz 319 ma graphics rgb sampling at 135 mhz 180 ma 1080p sampling at 148.5 mhz 214 ma digital i/o supply current i dvddio cvbs input sampling at 54 mhz 6 ma graphics rgb sampling at 78 mhz 15 ma graphics rgb sampling at 135 mhz 27 ma 1080p sampling at 148.5 mhz 48 ma pll supply current i pvdd cvbs input sampling at 54 mhz 13 ma graphics rgb sampling at 78 mhz 10 ma graphics rgb sampling at 135 mhz 10 ma 1080p sampling at 148.5 mhz 11 ma analog supply current i avdd cvbs input sampling at 54 mhz 99 ma scart rgb fb sampling at 54 mhz 269 ma graphics rgb sampling at 78 mhz 263 ma graphics rgb sampling at 135 mhz 286 ma 1080p sampling at 148.5 mhz 288 ma memory interface supply current i vddram cvbs input sampling at 54 mhz 17 ma power - down current i pwrdn 8 ma power - up time t pwrup 20 ms digital inputs input high voltage v ih 2 v input low voltage v il 0.8 v input current i in 10 a input capacitance c in 15 pf
data sheet ADV7802 rev. d | page 5 of 36 parameter 1 symbol test conditions min typ max unit digital outputs output high voltage 6 v oh i source = 0.4 ma 2.4 v output low voltage 6 v ol i sink = 3.2 ma 0.4 v high impedance leakage current i leak 10 a output capacitance c out 20 pf 1 temperature range t min to t max . 2 all adc linearity tests performed with part configured for component video input. 3 all adc linearity tests performed at input range of full scale ? 12.5% and at zero scale + 12.5%. 4 maximum inl and dnl specifications obtained with part configured for component video input. 5 guaranteed by characterization. 6 v oh and v ol levels obtaine d using default drive strength.
ADV7802 data sheet rev. d | page 6 of 36 video specifications av dd = 3.15 v to 3.45 v, dvdd = 1.75 v to 1.85 v , dvddio = 3.0 v to 3.6 v, dvddio_sdram = 2.4 v to 2.6 v (ddr), dvddio_sdram = 3.2 v to 3. 4 v (sdr), pvdd = 1.71 v to 1.89 v, t a = 0c to 85c, u nl ess otherwise noted. table 2 . parameter 1 symbol test conditions min typ max unit nonlinear specifications differential phase dp cvbs input ( modulated five - step ) 0.45 d egree s differential gain dg cvbs input ( modulated fiv e- step ) 0.45 % luma nonlinearity lnl cvbs input (modulated five - step ) 0.7 % noise specifications snr unweighted luma ramp 63 db luma flat field 64 db analog front - end crosstalk 60 db lock time specifications (sdp) horizon tal lock range 5 % vertical lock range 40 70 hz subcarrier lock range , f sc 0.8 k hz col or lock -i n time 60 lines sync depth range 2 20 200 % color burst range 1 200 % vertical lock time 300 ms horizontal lock time 100 l in es chroma specifications (sdp) chroma amplitude error 0.4 % chroma phase error 0.3 degrees chroma luma intermodulation 0.2 % 1 guaranteed by characterization. 2 nominal sync depth is 300 mv at 100% sync depth range .
data sheet ADV7802 rev. d | page 7 of 36 timing characteristi cs avdd = 3.15 v to 3.45 v, dvdd = 1.75 v to 1.85 v , dvddio = 3.0 v to 3.6 v, dvddio_s dram = 2.4 v to 2.6 v (ddr), dvddio_sdram = 3.2 v to 3.4 v (sdr), pvdd = 1.71 v to 1.89 v, t a = 0c to 85c, unless otherwise noted . table 3. parameter 1 symbol test conditions min typ max unit system clock and crystal crysta l nominal frequency 28.63636 mhz crystal frequency stability 50 ppm horizontal sync input frequency 14.8 90 khz llc frequency range 12.825 15 0 mhz i 2 c port sclk frequency 400 khz sclk min imum pulse width high t 1 0.6 s s clk minimum pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sda setup time t 5 100 ns sclk and sda rise time t 6 300 ns sclk and sda fall time t 7 300 ns setup time ( stop condition ) t 8 0.6 s fast i 2 c port 2 sclk frequency 3.4 mhz sclk minimum pulse width high t 1 60 ns sclk minimum pulse width low t 2 160 ns hold time (start condition) t 3 160 ns setup time (start condition) t 4 160 ns sda setup time t 5 10 ns sclk and sda rise time t 6 10 80 ns sclk and sda fall time t 7 10 80 ns setup time ( stop condition ) t 8 160 ns reset feature reset pulse width 5 ms clock outputs llc mark space ratio t 9 , t 10 45:55 55:45 % duty cycle p ixel port data and control outputs 3 data output transition time , sdr t 11 negative clock edge to start of valid data 4.5 ns data output transition time , sdr t 12 end of valid data to negative clock edge 0 ns data output transition time, sdr ( cp core) t 13 negative clock edge to start of valid data 2.5 ns data output transition time, sdr (cp core) t 14 end of valid data to negative clock edge 0.2 ns data and control inputs 4 input setup time (digital input port) t 17 hs_in1 , vs_in 1 , hs_in2, vs_in2 9.5 ns de_in, data inputs 2 ns input hold tim e (digital input port) t 18 hs_in1 , vs_in 1 , hs_in2, vs_in2 ?4 ns de_in, data inputs 0 .8 ns 1 guaranteed by characterization. 2 with a bus line load less than 100 pf. 3 t iming figures obtained using default drive strength value . 4 ttl input values are 0 v to 3 v , with rise/fall times 3 ns, measured between the 10% and 90% points .
ADV7802 data sheet rev. d | page 8 of 36 timing diagrams sda1/sda2 sclk1/sclk2 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 06654-004 figure 3. i 2 c timing llc t 9 t 10 t 12 t 11 p0 to p53, vs_out, hs_out, fld_de_out 06654-005 figure 4. pixel port and control sdr output timing (sd core) llc t 9 t 10 t 14 t 13 p0 to p53, vs_out, hs_out, fld_de_out 06654-011 figure 5. pixel port and control sdr output timing (cp core) t 18 t 17 clkin control inputs p30 to p39, p40 to p43, p44 to p53 hs_in1, vs_in1, hs_in2, vs_in2, de_in 06654-007 figure 6. digital input port and control input timing
data sheet ADV7802 rev. d | page 9 of 36 analog specification s av dd = 3.1 5 v to 3.45 v, dvdd = 1.75 v to 1.85 v , dvddio = 3.0 v to 3.6 v, dvddio_sdram = 2.4 v to 2.6 v (ddr), dvddio_sdra m = 3.2 v to 3.4 v (sdr ), pvdd = 1.7 1 v to 1.89 v, t a = 0c to 85c, unless otherwise noted . recommended analog input video signal range is 0.5 v to 1.6 v, typically 1 v p - p. recommended external clamp capacitor value is 0.1 f. table 4. parameter 1 , 2 test conditions min typ max unit clamp circuitry input impedance 3 clamps switched off 10 m? input impedance of pin 90 (fb) 20 k? cml 2.0 v adc full - scale level cml + 0.8 v adc zer o- scale level cml ? 0.8 v adc dynamic range 1.6 v clamp level (when locked) cvbs input cml ? 0.292 v scart rgb input (r, g, b signals) cml ? 0.3 v s - video input (y signal) cml ? 0.292 v s- video input (c signal) cml ? 0 v compo nent input (y signal) cml ? 0.3 v component input (pr, pb signals) cml ? 0 v pc rgb input (r, g, b signals) cml ? 0.3 v large clamp source current sdp only 0.75 ma large clamp sink current sdp only 0.9 ma fine clamp source current sdp only 17 a fine clamp sink current sdp only 17 a 1 the minimum/maximum specifications are guaranteed over 0c to 85c. 2 guaranteed by characterization. 3 except pin 90 (fb).
ADV7802 data sheet rev. d | page 10 of 36 absolute maximum ratings table 5. parameter rating avdd to agnd 4.0 v dvdd to dgnd 2.2 v pvdd to agnd 2.2 v dvddio to dgnd 4.0 v dvddio_sdram to dgnd_sdram (ddr) 2.7 v dvddio_sdram to dgnd_sdram (sdr) 4.0 v dvddio to avdd ?0.3 v to +0.3 v dvddio to dvdd ?0.3 v to +2 v dvddio_sdram to dvdd (ddr ) ?0.3 v to +2.5 v dvddio_sdram to dvdd (sdr ) ?0.3 v to +3.3 v avdd to pvdd ?0.3 v to +2 v avdd to dvdd ?0.3 v to +2 v dvddio to dvddio_sdram (ddr) ?0.3 v to +2 v dvddio to dvddio_sdram (sdr) ?0.3 v to +3.3 v avdd to dvddio_sdram (ddr) ?0.3 v to +2.5 v avdd to dvddio_sdram (sdr) ?0.3 v to +1.8 v digital inputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v dvddio_sdram inputs to dgnd_sdram dgnd_sdram ? 0.3 v to dvddio_sdram + 0.3 v analog inputs to agnd agnd ? 0.3 v to avdd + 0.3 v sclk/sda data pins to dvddio dvddio ? 0.3 v to dvddio + 3.6 v maximum junction temperature (t j max ) 125c storage temperature range ?65c to +150c infrared reflow soldering (20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal performance to reduce power consumption when using the part, the user is advised to turn off any unused adcs. the junction temperature must always stay below the maximum junction temperature (t j max ) of 125c. the following equation shows how to calculate the junction temperature: t j = t a max + ( ja w max ) where: t a max = 85c. ja = 21.0330c/w. w max = ((avdd i av d d ) + (dvdd i dvdd ) + (dvddio i dvddio ) + (pvdd i pvdd ) + (dvddio_sdram dvddio_sdram)). thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja 1 jc 2 unit 176-lead lqfp 21 7 c/w 1 4-layer pcb with solid ground plane. 2 4-layer pcb with solid ground plane (still air). esd caution
data sheet ADV7802 re v. d | page 11 of 36 pin configuration and function descripti ons ADV7802 top view (not to scale) pin 1 1 p13 2 p12 3 p11 4 p10 5 p9 6 p8 7 p7 8 p6 9 p5 10 p4 11 p3 12 p2 13 p1 14 p0 15 dvddio 16 dgnd 17 llc 18 cs/hs_out 19 sfl/sync_out 20 fld_de_out 21 vs_out 22 dgnd 23 dvdd 24 sdram_a11 25 sdram_a9 26 sdram_a8 27 sdram_a7 28 sdram_a6 29 sdram_a5 30 sdram_a4 31 sdram_a3 32 sdram_a2 33 sdram_a1 34 sdram_a0 35 dgnd 36 dvdd 37 dvddio_sdram 38 dgnd_sdram 39 sdram_a10 40 sdram_ba1 41 sdram_ba0 42 sdram_cs 43 sdram_ras 44 sdram_cas 89 agnd 90 fb 91 soy 92 sog 93 ain7 94 ain1 95 ain8 96 ain2 97 ain9 98 ain3 99 agnd 100 agnd 101 avdd 102 refout 103 cml 104 agnd 105 avdd 106 bias 107 capy1 108 capc1 109 capc2 110 ain10 111 ain4 112 ain11 113 ain5 114 ain12 115 ain6 116 aout 117 funct1 118 hs_in1 119 hs_in2 120 alsb 121 sda 122 sclk 123 int 124 vs_in2 125 vs_in1 126 de_in 127 p53 128 p52 129 p51 130 p50 131 p49 132 p48 133 p47 134 p46 135 p45 136 p44 137 dvdd 138 dgnd 139 p43 140 p42 141 p41 142 p40 143 dvddio 144 dgnd 145 p39 146 p38 147 p37 148 p36 149 p35 150 p34 151 p33 152 p32 153 p31 154 p30 155 p29 156 p28 157 p27 158 p26 159 dvdd 160 dgnd 161 p25 162 p24 163 p23 164 p22 165 p21 166 p20 167 p19 168 p18 169 p17 170 dvddio 171 dgnd 172 p16 173 p15 174 p14 175 dvdd 176 dgnd 45 sdram_we 46 sdram_ldm 47 dvddio_sdram 48 dgnd_sdram 49 sdram_ldqs 50 sdram_dq7 51 sdram_dq6 52 sdram_dq5 53 sdram_dq4 54 sdram_dq3 55 sdram_dq2 56 sdram_dq1 57 sdram_dq0 58 sdram_vref 59 dgnd 60 dvdd 61 dvddio_sdram 62 dgnd_sdram 63 sdram_dq15 64 sdram_dq14 65 sdram_dq13 66 sdram_dq12 67 sdram_dq11 68 sdram_dq10 69 sdram_dq9 70 sdram_dq8 71 sdram_udqs 72 sdram_udm 73 sdram_ck 74 sdram_ck 75 sdram_cke 76 dvdd 77 dgnd 78 clkin 79 dvddio 80 xtal 81 xtal1 82 dgnd 83 reset 84 pvdd 85 agnd 86 elpf1 87 pvdd 88 elpf2 06654-003 figure 7 . pin configuration
ADV7802 data sheet rev. d | page 12 of 36 table 7 . pin function descriptions pin no. mnemonic type 1 description 1 to 14, 155 to 158, 161 to 169, 172 to 174 p0 to p29 o video pixel output port. see figu re 7 for details on pin mapping. 15, 79, 143, 170 dvddio p digital input/output supply voltage (3.3 v). 16, 22, 35, 59, 77, 82, 138, 144, 160, 171 , 176 dgnd gnd digital ground. 17 llc o line - locked output clock for the pixel data. 18 cs/ hs_out o horiz ontal synchronization or composite synchronization signal. this signal can be selected while in sdp mode. 19 sfl/sync_out o subcarrier frequency lock. this pin contains a serial output stream, which can be used to lock the subcarrier frequency when this d ecoder is connected to any digital video encoder from analog devices, inc. sync_out is the sliced synchronization output signal available only in cp mode. 20 fld_de_out o field synchronization output signal (all interlaced video modes). this pin also can be enabled as a data enable signal (de) to allow direct connection to an hdmi ? /dvi tx ic. 21 vs_out o vertical synchronization output signal (sdp and cp m odes). 23, 36, 60, 76, 137, 159, 175 dvdd p digital core supply voltage (1.8 v). 24 to 34, 39 sdram _a0 to sdram_a11 o address outputs. interface to e xternal ram address l ines. see figure 7 for details on pin mapping. 37, 47, 61 dvddio_sdram p external m emory interface digital input/output supply (ddr 2.5 v or sdr 3.3 v). 38, 48, 62 dgnd_sdram gnd external memory interface digital gnd. 40, 41 sdram_ba1 to sdram_ba0 o bank address outputs. interface to extern al ram bank address line s. 42 sdram_cs o chip select. sdram_cs enables and disables the command decoder on the ram. 43 sdram_ras o row address select command sig nal. sdram_ras , sdram_cas , sdram_we , and sdram_cs define the command to the ram. 44 sdram_cas o column address select command s ignal. sdram_ras , sdram_cas , sdram_we , and sdram_cs define the command to the ram. 45 sdram_we o write e nable output command s ignal. sdram_ras , sdram_cas , sdram_we , and sdram_cs define the command to the ram. 46, 72 sdram_ldm, sdram_udm o data mask o utput. data is m asked when dm is high, for writing data to the external ram. ldm corresponds to the data on sdram_dq0 to sdram_dq7, and udm corresponds to the data on sdram_dq8 to sdram_dq15. 49 sdram_ldqs i/o lower data strobe pin. data strobe pins are used for the ram interface. this is an output with read data and an input with write data. it is edge aligned with write data and centered in read data. sdram_ ldqs corresponds to the data on sdram_dq0 to sdram_dq7. 50 to 57, 63 to 70 sdram_dq0 to sdram_dq15 i/o data bus. interface to e xtern al ram 16 -b it d ata b us. see figure 7 for details on pin mapping. 58 sdram_vref p 1.25 v reference for the ddr sdram interface or 1.65 v for sdr. 71 sdram_udqs i/o upper data strobe pin. data strobe pins for the ram interface. t his is an output with read data and an input with write data. it is edge aligned with write data and centered in read data. sdram_udqs corresponds to the data on sdram_dq8 to sdram_dq16. 73, 74 sdram_ ck , sdram_ck o differential clock out put. all address and control output signals to the ram shoul d be sampled on the positive edge of sdram_ck and on the negative edge of sdram_ck . 75 sdram_cke o clock enabl e. this pin is used as an enable to the clock signals of the exter nal ram. 78 clkin i clock input signal. used in 24 - bit digital input mode (for example, processing 24- bit rgb data from a dvi/hdmi rx ic and also in digital cvbs input mode ). 80 x tal i crystal input. input pin for 28.63636 mhz crystal . 81 x tal1 o crysta l output. this pin should be connected to the 28.63636 mhz crystal .
data sheet ADV7802 re v. d | page 13 of 36 pin no. mnemonic type 1 description 83 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the ADV7802 circuitry. 84, 87 pvdd p pll supply voltage (1.8 v). 85, 89 , 99, 100, 104 agnd gnd analog ground. 86, 88 elpf1, elpf2 i external loop filter. the recommend external loop filter must be connected to each elpf pin (see figure 8 ). 90 fb i scart fast blank input. 91 soy i sync on l uma input. used in embedded synchronization mode. 92 sog i sync on green input. used in embedded synchronization mode. 93 to 98, 110 to 115 ain1 to ain12 i analog video input channels. see figure 7 for details on pin mapping. 101, 105 avdd p analog supply voltage (3.3 v). 102 refout o internal voltage reference output. 103 cml o common - mode level pin used for the internal adcs. 106 bias o ex ternal bias setting pin. connect the recommended resistor (1.35 k ? ) b etween the pin and ground. 107 capy1 i adc capacitor network. 108, 109 capc1, capc2 i adc capacitor network. 116 aout o analog monitor output. 117 funct1 i scart function select inp ut. 118 hs_in1 i horizontal synchronization input signal. used in cp mode for 5 - wire timing mode. 119 hs_in2 i/o horizontal synchronization input signal. used in 24 - bit digital input mode port mode (for example, processing 24 - bit rgb data from an hdmi r x ic). hs_in2 in conjunction with vs_in2 can be configured as a fast i 2 c interface for teletext data extraction. hs_in2 is used as the i 2 c port serial clock i nput. 120 alsb i alsb selects the i 2 c address for the ADV7802 control. alsb set to logic 0 config ur es the address for a write to the input/output port of 0x40. alsb set to l ogic 1 configures the address for a write to the input/output port of 0x42. 121 sda i/o i 2 c port serial data input/output pin. 122 sclk i i 2 c port serial clock input (maximum c lock rate of 400 khz). 123 int o interrupt output. this pin can be active low or active high. when sdp/cp status bits change, this pin triggers. the set of events that triggers an interrupt is under user control. 124 vs_in2 i/o vertica l synchronization input signal. used in 24 - bit digital input port mode (for example, processing 24 - bit rgb data from an dvi/hdmi rx ic ). vs_in2 in conjunction with hs_in2 can be configured as a fast i 2 c interface for teletext data extraction. vs_in2 is use d as the i 2 c port serial data input/output pins. 125 vs_in1 i vertical synchronization input s ignal. used in cp mode for 5 - wire timing mode. 126 de_in i data enable input signal. used in 24 - bit digital input port mode (for example, processing 24 - bit rgb data from an dvi/hdmi rx ic). 127 to 136, 139 to 142, 145 to 154 p30 to p53 i/o video pixel input/output port. see figure 7 for details on pin mapping. 1 gnd = ground, i = input, i/o = input/output, o = output, p = power.
ADV7802 data sheet rev. d | page 14 of 36 theory of operation key features the ADV7802 is a high quality, single - chip, multiformat 3d comb filter video decoder and graphics digitizer. key features of the device include ? four noise shaped v ide o (nsv ?) 12- bit adcs ? ntsc/pal/secam v ideo d ecoder ? adaptive 3d c omb filtering ? 3 d digital noise red uction ? advanced frame t ime -b ase c orrection (tbc) ? composite, s -v ideo, yp rpb / rgb scart support ? yp rpb c omponent hd and rgb graphics i nput s upport ? 36- bit digital yp rpb /rgb output supporting 12 -b it d eep c olor analog front end the adv780 2 analog front end comprise s four 12 - bit nsv adcs that digitize the analog video signal befo re applying it to the sdp or cp . the front end includes a 12 - channel input mux that enables multiple video signals to be applied to the adv780 2 without the r equirement of an external mux. current and voltage cla mps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. the adcs are configured to run up to 4 oversampling mode when decoding composite and s -v ideo inputs or component s up to 525 i and 625 i. f or 525p an d 625p, 2 oversampling is available. all other video standards are 1 oversampled. in oversampling the video signals, a reduction in the cost and complexity of external anti aliasing filters can be obtained with the benefit of an increased signal - to - noise ratio (snr). optional internal anti aliasing filters with programmable bandwidth are positioned in front of each adc. these filters can be used to band - limit standard definition (sd) video signals, removing spurious, out - of - band noise. the adv780 2 ca n support simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed , and the output is under the control of i 2 c registers and the fast bl ank pin. analog front -e nd features include ? four 15 0 mhz, nsv, 12 - bit adcs that enable true 12 - bit video decoding ? 12- channel analog input mux that enables multiple source connections without the requirement of an external mux ? four current and voltage clam p control loops that ensure that any dc offsets are removed from the video signal ? scart functionality and sd rgb overlay on cvbs controlled by fast blank input ? scart source switching detection through funct1 input ? four pr ogrammable antialias filters on sta nd ard de finition video signals and enhance definition ? cvbs monitor output s tandard definition p rocessor the s tandard definition processor ( sdp ) is capable of decoding a larg e selection of baseband video signals in composite, s -v ideo , and yuv formats. the video standards supported by the sdp include pal, pal 60, pal m, pal n, pal nc , ntsc m/j, ntsc 4.43, and secam . the adv780 2 can automatically detect the video standard and process it accordingly. the ADV7802 can process video up to 525 p /625p formats. the sd p has a 3d temporal comb filter and a five - line super adaptive 2d comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. the sdp has an if filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner saw filter. the sdp has specific lumi- nance and chrominance p arameter control s for brightness, contrast, saturation, and hue. the adv 7802 implements a patented adaptive digital line length tracking ( adllt ) algorithm to track varying video line lengths from sources such as a vcr. adllt enables the ADV7802 to track a nd decode poor quality video sources ( such as vcrs ) and noisy sources (such as tuner outputs, vc r players, and camcorders ). frame tbc ensures stable clock synchronization between the decoder and the downstream devices. the sdp also contains both a luma tra nsient improvement ( lti ) and a chroma transient improvement ( cti ) processor. this processor increases the edge rate on the luma and chroma transitions, resulting in a sharper video image.
data sheet ADV7802 re v. d | page 15 of 36 the sdp has a m acrovision ? detection circuit, which allows type i, type ii, and type iii m acrovision protection levels. the decoder is also fully robust to all macrovision signal inputs. sdp features include ? advanced adaptive 3d comb with concurrent 3d noise reduction (using external ddr sdram memory) ? a daptive 2d five - li ne comb filters for ntsc and pal that give superior chrominance and luminance separation for composite video ? full automatic detection and autoswitching of all worldwide standards (pal, ntsc, and secam) ? automatic gain control with white peak mode that ensu res that the video is always processed without loss of the video processing range ? proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners ? if filter block that compensates for high frequency luma attenuation due to tu ner saw filter ? lti and cti ? vertical and horizontal programmable luma peaking filters ? true full 12 - bit deep color processing path from front to back end in 4:4:4/4:2:2 rgb/ycrcb formats ? 4 oversampling (54 mhz) for cvbs, s -v ideo, and yuv modes ? line - locke d clock output (llc) ? free run output mode that provides stable timing when no video input is present ? internal color bar test pattern ? advance d tbc with frame synchronization , which ensures nominal clock and data for nonstandard input ? interlace - to -progressiv e conversion for 525i and 625i formats , enabling direct drive of hdmi t x device s ? color controls that include hue, brightness, saturation , and contrast ? differential gain (dg) , typically 0.45% ? differential phase (dp) , typically 0.45 vbi data processor th e vbi data p rocessor ( vdp ) of the adv780 2 is capable of slicing multiple vertical blanking interval data standards on sd video and component video. th e vdp decodes the vbi data on the incoming cvbs/yc or yuv d ata processed by the sdp core. it can also deco de vbi data on the luma channel of yuv data processed through the cp core. the vdp can process a variety of vbi data standards , such as ? teletext ? video programming system (vps) ? vertical interval time codes (vitc) ? closed captioning (cc) and extended data ser vice (eds) ? wide screen signaling (wss) ? copy generation management system (cgms, cgms type b) ? gemstar? 1/2 electronic program guide compatible ? extended data service (sds); the data extracted can be read back over a fast i 2 c interface component processor the c omponent p rocessor ( cp ) is capable of decoding and digi - tizing a wide range of component video formats in any color space. the cp can accept video data from the analog front end or from the hdmi receiver. component video standards supported by the cp include 525i, 625i, 525p, 625p, 720p, 1080i , 1080p , and vga (up to s xga at 75 hz), and many other standards. a fully programmable any - to - any , 3 3 color space conversion (csc) matrix is placed before the cp. this enables yp rpb - to - rgb and rgb - to - ycrcb con versions of video data coming from the analog front end or from the hdmi receiver. many other standards of color space can be implemented using the color space converter. the cp of the ADV7802 contains an automatic gain control ( agc ) block. the agc is foll owed by a clamp circuit that ensures that the video signal is clamped to the correct blanking level. automatic adjustments within the cp include gain (contrast) and offset (brightness). manual adjustment controls are also supported. in cases where no embed ded synchroni - zation is preset, the video gain can be set manually.
ADV7802 data sheet rev. d | page 16 of 36 the cp co ntains circuitry to enabl e the detection of macrovisi on encoded yp rpb signals for 525i, 625i, 525p, and 625p . it is designed to be fully robust to these types of signals. cp feat ures include ? 525i, 625i, 525p, 625p, 720p, 108 0i , 1080p , and many other hdtv formats supported ? automatic adjustments including gain (contrast) and offset (brightness); manual adjustment controls are also supported ? support for analog component yprpb and rg b video formats with embedded synchronization or with separate hs, vs, or cs ? any - to - any, 3 3 color space conversion matrix that supports ycrcb - to - rgb and rgb - to - ycrcb , f ully programmable or preprogrammable configurations ? synchronization source polarity d etector (sspd) that determines the source and polarity of the synchronization signals that accompany the input video ? macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) ? free run output mode that provides stable timing wh en no video input is present ? arbitrary pixel sampling suppor t for nonstandard video sources ? 1 35 mhz graphics processing , support ing rgb input resolutions up to 1280 1024 at 7 5 hz ? automatic or manual clamp - and - gain controls for graphics modes ? contrast, brightness, hue , and saturation controls ? 32- phase dll that allows optimum pixel clock sampling ? automatic detection of synchronization source and polarity by sspd block ? standard identification enabled by stdi block ? rgb that can be color sp ace converted to ycrcb and deci ma ted to a 4:2:2 format for video centric back - end ic interfacing ? data enable (de) output signal supplied for dire ct connection to hdmi/dvi tx ic ? arbitrary pixel sampling support for nonstandard video sources additional f eatures the ADV7802 a lso includes ? hs, vs, field , and de output signals with programmable position, polarity, and width ? programmable interrupt request output pin ( int ) that signals sdp/cp status changes ? t wo i 2 c host port interface (control and vbi) support ? in tegrated programmable antialiasing filters ? 176- lead, 26 mm 26 mm, rohs - compliant lqfp for more detailed product information about the adv7 802, contact a local a nalog d evices sales representative. single data rate (sd r) the ADV7802 uses sdr external memo ry 1 for 3d comb, frame synchronizer operation , or 3d - dnr nonconcurrent operation. ? 64 mb sdr sdram minimum memory requirement . ? the m emory architecture required is four banks of 1 m b 16. ? speed grade of 133 mhz at cas latency (cl) 3 is required . ? 22 ? series termination resistors are recommended for this configuration . ? recommended memory that is compatible with the ADV7802 includes the mt48lc4m16a2 from micron . double d ata r ate ( ddr ) the ADV7802 uses ddr external memory 1 for simultaneous 3d comb, frame synchronizer , and 3d - dnr operation. ? 128 mb ddr s dram minimum memory requirement . ? the memory architecture required is four b anks of 2 mb 1 6. ? speed grade of 133 mhz at cas latency ( cl ) 2.5 is required . ? termination resi stors not recommended for this configuration . ? recommended memory that is compatible with the adv780 2 includes k4h281638b - tcb0 from samsung, the mt46v8m16 - tgp - 75 f rom m icron, and the hyb25d128160ce -6 from infineo n. 1 when e xternal memory is not connected, io map register 0x29[4] should be set high directly after reset.
data sheet ADV7802 re v. d | page 17 of 36 recommended external loop filter compone nts the external loop filter components for the elpf pins should be placed as close as possible to the respective pins. figure 8 shows the recommended component values. 1.69k? 82nf 10nf pvdd = 1.8v pin 86 (elpf1) 160? 820nf 39nf pvdd = 1.8v pin 88 (elpf2) 06654-008 figure 8. elpf components
ADV7802 data sheet rev. d | page 18 of 36 typical connection diagrams ADV7802 06654-009 figure 9. typical connection diagram (external ddr memory)
data sheet ADV7802 rev. d | page 19 of 36 ADV7802 0 6654-010 figure 10. typical connection diagram (external sdr memory)
ADV7802 data sheet rev. d | page 20 of 36 0 6654-012 u2 ADV7802 figure 11. typical connection diagram (no external memory)
data sheet ADV7802 re v. d | page 21 of 36 pixel input/output f ormatting there are several modes in which the ADV7802 pixel port can be configured. these modes are under the i 2 c control of op_format_sel[5:0]. pixel data output mo des highlights the ADV7802 has a flexib le pixel port, which can be configured in a variety of formats to accommodate downstream ics. see table 8 and table 9 for more information on each mode. the out put pixel port features include ? 8- /10 - /12 - bit itu - r bt.656 4:2:2 ycrcb with embedded time codes and/or hs_out , vs_out , and fld_de_out pin timing ? 16- /20 - /24 - bit ycrcb with embedded time codes and/or hs_out, vs_out, and fld_de_out pin timing ? 24- /30 - /36 - /48 - bit ycrcb/rgb with embedded time codes and /or hs_out, vs_out, and fld_de_out pin timing ? ddr 8 - /10 - /12 - bit 4:2:2 ycrcb for all standards ? ddr 12 - /24 - /30 - /36 - bit 4:4:4 rgb for all standards ? 48- bit 4:4:4 rgb dual - pin mode ? simultaneous output modes 16 - /20 - /24 - bit ycrcb and 8- /10 - /12 - bit 4:2:2 ycrcb up to 525i/525p and 625i/625p digita l video input port h ighlights the ADV7802 contains a 24 - bit digital input port. the m ain features are as follows: ? support for 24 - bit rgb input data from the dvi/hdmi rx ic , pass - through , or output converted to 4:2:2 ycr cb ? support for 24 - bit 4:4:4, 16 - /20 - bit 4:2:2 525i, 625i, 525p, 625p, 720p , 1080i , 1080p, and vga to s xg a at 75 hz input data from the dvi/hdmi rx ic chip, pass - through , or output converted to 4:2:2 ycrcb ? dedicated synchronization and pixel port inputs
ADV7802 data sheet rev. d | page 22 of 36 t able 8. sdr pixel port output modes 1, 2 op_format_sel [5:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 pixel output 8- bit sdr itu - 656 mode 1 10- bit sdr itu - 656 mode 1 12- bit sdr itu - 656 mode 1 12- bit sdr itu - 656 mode 2 12- bit sdr itu - 656 mode 3 16- bit sdr itu - 656 4 :2:2 mode 1 20- bit sdr itu - 656 4:2:2 mode 1 24- bit sdr it u- 656 4:2:2 mode 1 p53 p52 p51 p50 p49 p48 p47 p46 p45 p44 p43 p42 p41 p40 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 p29 y7, cb7, cr7 y9, cb9, cr9 y11, cb11, cr11 y11, cb11, cr11 y11, cb11, cr11 y7 y9 y11 p28 y6, cb6, cr6 y8, cb8, cr8 y 10, cb10, cr10 y10, cb10, cr10 y10, cb10, cr10 y6 y8 y10 p27 y5, cb5, cr5 y7, cb7, cr7 y9, cb9, cr9 y9, cb9, cr9 y9, cb9, cr9 y5 y7 y9 p26 y4, cb4, cr4 y6, cb6, cr6 y8, cb8, cr8 y8, cb8, cr8 y8, cb8, cr8 y4 y6 y8 p25 y3, cb3, cr3 y5, cb5, cr5 y7, cb7, cr7 y7, cb7, cr7 y7, cb7, cr7 y3 y5 y7 p24 y2, cb2, cr2 y4, cb4, cr4 y6, cb6, cr6 y6, cb6, cr6 y6, cb6, cr6 y2 y4 y6 p23 y1, cb1, cr1 y3, cb3, cr3 y5, cb5, cr5 y5, cb5, cr5 y5, cb5, cr5 y1 y3 y5 p22 y0, cb0, cr0 y2, c b2, cr2 y4, cb4, cr4 y4, cb4, cr4 y4, cb4, cr4 y0 y2 y4 p21 z y1, cb1, cr1 y3, cb3, cr3 z y3, cb3, cr3 z y1 y3 p20 z y0, cb0, cr0 y2, cb2, cr2 z y2, cb2, cr2 z y0 y2 p19 z z y1, cb1, cr1 y3, cb3, cr3 z cb7, cr7 cb9, cr9 cb11, cr11 p18 z z y0, cb0, cr0 y2, cb2, cr2 z cb6, cr6 cb8, cr8 cb10, cr10 p17 z z z y1, cb1, cr1 z cb5, cr5 cb7, cr7 cb9, cr9 p16 z z z y0, cb0, cr0 z cb4, cr4 cb6, cr6 cb8, cr8 p15 z z z z z cb3, cr3 cb5, cr5 cb7, cr7 p14 z z z z z cb2, cr2 cb4, cr4 cb6, cr6 p13 z z z z z cb1, cr 1 cb3, cr3 cb5, cr5 p12 z z z z z cb0, cr0 cb2, cr2 cb4, cr4 p11 z z z z z z cb1, cr1 cb3, cr3 p10 z z z z z z cb0, cr0 cb2, cr2
data sheet ADV7802 re v. d | page 23 of 36 op_format_sel [5:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 pixel output 8- bit sdr itu - 656 mode 1 10- bit sdr itu - 656 mode 1 12- bit sdr itu - 656 mode 1 12- bit sdr itu - 656 mode 2 12- bit sdr itu - 656 mode 3 16- bit sdr itu - 656 4 :2:2 mode 1 20- bit sdr itu - 656 4:2:2 mode 1 24- bit sdr it u- 656 4:2:2 mode 1 p9 z z z z z z z y1 p8 z z z z z z z y0 p7 z z z z z z z z p6 z z z z z z z z p5 z z z z z z z cb1, cr1 p4 z z z z z z z cb0, cr0 p3 z z z z y1, cb1, cr1 z z z p2 z z z z y0, cb0, cr0 z z z p1 z z z z z z z z p0 z z z z z z z z 1 it is recommended to print this table (located on this page and the following two p age s ) and read as one horizontal expanded table. 2 blank cells are not p opulated areas.
ADV7802 data sheet rev. d | page 24 of 36 op_format_sel [5:0] 0x08 0x09 0x0a 0x2c 0x2d 0x2e 0x0b 0x0c 0x0d pixel output 24- bit sdr itu - 656 4:2:2 mode 2 24- bit sdr itu - 656 4:2:2 mo de 3 24- bit sdr 4:4:4 mode 1 24- bit sdr 4:4:4 mode 2 24- bit sdr 4:4:4 mode 3 24- bit sdr 4:4:4 mode 1 30- bit sdr 4:4:4 mode 1 36- bit sdr 4:4:4 mode 1 36- bit sdr 4:4:4 mode 2 p53 g1 g3 p52 g0 g2 p51 z g1 p50 z g0 p49 z z p48 z z p47 z z p46 z z p45 b1 b3 p44 b0 b2 p43 z b1 p42 z b0 p41 z z p40 z z p39 z z p38 z z p37 r1 r3 p36 r0 r2 p35 z r1 p34 z r0 p33 z z p32 z z p31 z z p30 z z p29 y11 y11 g7 g7 r7 b7 g9 g11 g11 p28 y10 y10 g6 g6 r6 b6 g8 g10 g10 p27 y9 y9 g5 g5 r5 b5 g7 g9 g9 p26 y8 y8 g4 g4 r4 b4 g6 g8 g8 p25 y7 y7 g3 g3 r3 b3 g5 g7 g7 p24 y6 y6 g2 g2 r2 b2 g4 g6 g6 p23 y5 y5 g1 g1 r1 b1 g3 g5 g5 p22 y4 y4 g0 g0 r0 b0 g2 g4 g4 p21 y3 z z b7 g7 r7 g1 g3 z p20 y2 z z b6 g6 r6 g0 g2 z p19 cb11, cr11 cb11, cr11 b7 b5 g5 r5 b9 b11 b11 p18 cb10, cr10 cb10, cr10 b6 b4 g4 r4 b8 b10 b10 p17 cb9, cr9 cb9, c r9 b5 b3 g3 r3 b7 b9 b9 p16 cb8, cr8 cb8, cr8 b4 b2 g2 r2 b6 b8 b8 p15 cb7, cr7 cb7, cr7 b3 b1 g1 r1 b5 b7 b7 p14 cb6, cr6 cb6, cr6 b2 b0 g0 r0 b4 b6 b6 p13 cb5, cr5 cb5, cr5 b1 r7 b7 g7 b3 b5 b5 p12 cb4, cr4 cb4, cr4 b0 r6 b6 g6 b2 b4 b4 p11 cb3, cr 3 z z r5 b5 g5 b1 b3 z p10 cb2, cr2 z z r4 b4 g4 b0 b2 z
data sheet ADV7802 re v. d | page 25 of 36 op_format_sel [5:0] 0x08 0x09 0x0a 0x2c 0x2d 0x2e 0x0b 0x0c 0x0d pixel output 24- bit sdr itu - 656 4:2:2 mode 2 24- bit sdr itu - 656 4:2:2 mo de 3 24- bit sdr 4:4:4 mode 1 24- bit sdr 4:4:4 mode 2 24- bit sdr 4:4:4 mode 3 24- bit sdr 4:4:4 mode 1 30- bit sdr 4:4:4 mode 1 36- bit sdr 4:4:4 mode 1 36- bit sdr 4:4:4 mode 2 p9 z y3 r7 r3 b3 g3 r9 r11 r11 p8 z y3 r6 r2 b2 g2 r8 r10 r10 p7 cb1, cr1 y1 r5 r1 b1 g1 r7 r9 r9 p6 cb0, cr0 y0 r4 r0 b0 g0 r6 r8 r8 p5 z cb3, cr3 r3 z z z r5 r7 r7 p4 z cb2, cr2 r2 z z z r4 r6 r6 p3 y1 cb1, cr1 r1 z z z r3 r5 r5 p2 y0 cb0, cr0 r0 z z z r2 r4 r4 p1 z z z z z z r1 r3 z p0 z z z z z z r0 r2 z
ADV7802 data sheet rev. d | page 26 of 36 op_format_sel [5:0] 0x28 0x29 0x2a 0x2b 0x0e 0x0f pixel output 16- bit and 8 - bit sdr 4:2:2 m ode 1 parallel output 20- bit and 10 - bi t sdr 4:2:2 mode 1 parallel output 24- bit and 12 - bit sdr 4:2:2 mode 1 parallel output 24- bit and 12 - bit sdr 4:2:2 mode 2 parallel output 48- bit dual pin mode 0 48- bit dual pin mode 1 clock rise clock rise clock fall p53 main y1 main y3 g7 -1 g7 -1 p52 main y0 main y2 g6 -1 g6 -1 p51 z main y1 g5 -1 g5 -1 p50 z main y0 g4 -1 g4 -1 p49 z z g3 -1 g3 -1 p48 z z g2 -1 g2 -1 p47 z z g1 -1 g1 -1 p46 z z g0 -1 g0 -1 p45 main cb1, cr1 main cb3, cr3 b7 -1 b7 -1 p44 main cb0, cr0 main cb2, cr2 b6 -1 b6 -1 p43 z main cb1, cr1 b5 -1 b5 -1 p42 z main cb0, cr0 b4 -1 b4 -1 p41 z z b3 -1 b3 -1 p40 z z b2 -1 b2 -1 p39 z z b1 -1 b1 -1 p38 z z b0 -1 b0 -1 p37 aux y1, cb1, cr1 aux y3, cb3, cr3 r7 - 1 r7 - 1 p36 aux y0, cb0, cr0 aux y2, cb2, cr2 r6 - 1 r6 - 1 p35 z aux y1, cb1, cr1 r5 - 1 r5 - 1 p34 z aux y0, cb0, cr0 r4 -1 r4 -1 p33 z z r3 -1 r3 -1 p32 z z r2 -1 r2 -1 p31 z z r1 -1 r1 -1 p30 z z r0 -1 r0 -1 p29 main y7 main y9 main y11 main y11 g7 -0 g7 -0 p28 main y6 main y8 m ain y10 main y10 g6 -0 g6 -0 p27 main y5 main y7 main y9 main y9 g5 - 0 g5 - 0 p26 main y4 main y6 main y8 main y8 g4 -0 g4 -0 p25 main y3 main y5 main y7 main y7 g3 - 0 g3 - 0 p24 main y2 main y4 main y6 main y6 g2 -0 g2 -0 p23 main y1 main y3 main y5 main y5 g1 -0 g1 -0 p22 main y0 main y2 main y4 main y4 g0 -0 g0 -0 p21 z main y1 main y3 z z z p20 z main y0 main y2 z z z p19 main cb7, cr7 main cb9, cr9 main cb11, cr11 main cb11, cr11 b7 -0 b7 -0 p18 main cb6, cr6 main cb8, cr8 main cb10, cr10 main cb10, cr10 b6 -0 b6 -0 p17 main cb5, cr5 main cb7, cr7 main cb9, cr9 main cb9, cr9 b5 -0 b5 -0 p16 main cb4, cr4 main cb6, cr6 main cb8, cr8 main cb8, cr8 b4 - 0 b4 - 0 p15 main cb3, cr3 main cb5, cr5 main cb7, cr7 main cb7, cr7 b3 - 0 b3 - 0 p14 main cb2, cr2 main cb4, cr4 main cb6, cr6 main cb6, cr6 b2 -0 b2 -0 p13 main cb1, cr1 main cb3, cr3 main cb5, cr5 main cb5, cr5 b1 -0 b1 -0 p12 main cb0, cr0 main cb2, cr2 main cb4, cr4 main cb4, cr4 b0 -0 b0 -0 p11 z main cb1, cr1 main cb3, cr3 z z z p10 z main cb0, cr0 m ain cb2, cr2 z z z
data sheet ADV7802 re v. d | page 27 of 36 op_format_sel [5:0] 0x28 0x29 0x2a 0x2b 0x0e 0x0f pixel output 16- bit and 8 - bit sdr 4:2:2 m ode 1 parallel output 20- bit and 10 - bi t sdr 4:2:2 mode 1 parallel output 24- bit and 12 - bit sdr 4:2:2 mode 1 parallel output 24- bit and 12 - bit sdr 4:2:2 mode 2 parallel output 48- bit dual pin mode 0 48- bit dual pin mode 1 p9 aux y7, cb7, cr7 aux y9, cb9, cr9 aux y11, cb11, cr11 aux y11 , cb11, cr11 r7 -0 r7 -0 p8 aux y6, cb6, cr6 aux y8, cb8, cr8 aux y10, cb10, cr10 aux y10, cb10, cr10 r6 -0 r6 -0 p7 aux y5, cb5, cr5 aux y7, cb7, cr7 aux y9, cb9, cr9 aux y9, cb9, cr9 r5 -0 r5 -0 p6 aux y4, cb4, cr4 aux y6, cb6, cr6 aux y8, cb8, cr8 aux y8, cb8, cr8 r4 -0 r4 -0 p5 aux y3, cb3, cr3 aux y5, cb5, cr5 aux y7, cb7, cr7 aux y7, cb7, cr7 r3 -0 r3 -0 p4 aux y2, cb2, cr2 aux y4, cb4, cr4 aux y6, cb6, cr6 aux y6, cb 6, cr6 r2 -0 r2 -0 p3 aux y1, cb1, cr1 aux y3, cb3, cr3 aux y5, cb5, cr5 aux y5, cb5, cr5 r1 -0 r1 -0 p2 aux y0, cb0, cr0 aux y2, cb2, cr2 aux y4, cb4, cr4 aux y4, cb4, cr4 r0 -0 r0 -0 p1 z aux y1, cb1, cr1 aux y3, cb3, cr3 z z z p0 z aux y0, cb0, cr0 au x y2, cb2, cr2 z z z
ADV7802 data sheet rev. d | page 28 of 36 table 9. ddr pixel port output modes 1, 2 op_format_sel [5:0] 0x10 0x11 0x12 0x13 0x14 pixel output 8- bit ddr itu - 656 10- bit ddr itu - 656 12- bit ddr ycrcb 4:2:2 mode 1 12- bit ddr ycrcb 4:2:2 mode 2 12- bit ddr ycrcb 4:2:2 mode 3 clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall p53 p52 p51 p50 p49 p48 p47 p46 p45 p44 p43 p42 p41 p40 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 p29 cb7, cr7 y7 cb9, cr9 y9 cb11, cr11 y11 cb11, cr11 y11 cb11, cr11 y11 p28 cb6, cr6 y6 cb8, cr8 y8 cb10, cr10 y10 cb10, cr10 y10 cb10, cr10 y10 p27 cb5, cr5 y5 cb7, cr7 y7 cb9, cr9 y9 cb9, cr9 y9 cb9, cr9 y9 p26 cb4, cr4 y4 cb6, cr6 y6 cb8, cr8 y8 cb8, cr8 y8 cb8, cr8 y8 p25 cb3, cr3 y3 cb5, cr5 y5 cb7, cr7 y7 cb7, cr7 y7 cb7, cr7 y7 p24 cb2, cr2 y2 cb4, cr4 y4 cb6, cr6 y6 cb6, cr6 y6 cb6, cr6 y6 p23 cb1, cr1 y1 cb3, cr3 y3 cb5, cr5 y5 cb5, cr5 y5 cb5, cr5 y5 p22 cb0, cr0 y0 cb2, cr2 y2 cb4, cr4 y4 cb4, cr4 y4 cb4, cr 4 y4 p21 z z cb1, cr1 y1 cb3, cr3 y3 z z cb3, cr3 y3 p20 z z cb0, cr0 y0 cb2, cr2 y2 z z cb2, cr2 y2 p19 z z z z cb1, cr1 y1 cb3, cr3 y3 z z p18 z z z z cb0, cr0 y0 cb2, cr2 y2 z z p17 z z z z z z cb1, cr1 y1 z z p16 z z z z z z cb0, cr0 y0 z z p15 z z z z z z z z z z p14 z z z z z z z z z z p13 z z z z z z z z z z p12 z z z z z z z z z z p11 z z z z z z z z z z p10 z z z z z z z z z z
data sheet ADV7802 re v. d | page 29 of 36 op_format_sel [5:0] 0x10 0x11 0x12 0x13 0x14 pixel output 8- bit ddr itu - 656 10- bit ddr itu - 656 12- bit ddr ycrcb 4:2:2 mode 1 12- bit ddr ycrcb 4:2:2 mode 2 12- bit ddr ycrcb 4:2:2 mode 3 clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall p9 z z z z z z z z z z p8 z z z z z z z z z z p7 z z z z z z z z z z p6 z z z z z z z z z z p5 z z z z z z z z z z p4 z z z z z z z z z z p3 z z z z z z z z cb1, cr1 y1 p2 z z z z z z z z cb0, cr0 y0 p1 z z z z z z z z z z p0 z z z z z z z z z z 1 it is recommended to print this table (located on this page and the following three p age s ) and read as one horizontal expanded table. 2 blank cells are not populated areas.
ADV7802 data sheet rev. d | page 30 of 36 op_format_sel [5:0] 0x15 0x1a 0x1b 0x1c pixel output 12- bit ddr rgb 4:4:4 24- bit ddr rgb (clk/2) 30- bit dd r rgb (clk/2) 36- bit ddr rgb (clk/2) mode 1 clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall p53 g1 -0 g1 -1 p52 g0 -0 g0 -1 p51 z z p50 z z p49 z z p48 z z p47 z z p46 z z p45 b1 -0 b1 -1 p44 b0 -0 b0 -1 p43 z z p42 z z p41 z z p40 z z p39 z z p38 z z p37 r1 -0 r1 -1 p36 r0 -0 r0 -1 p35 z z p34 z z p33 z z p32 z z p31 z z p30 z z p29 b7 r3 g7 -0 g7 -1 g9 -0 g9 -1 g11 -0 g11 -1 p28 b6 r2 g6 -0 g6 -1 g8 -0 g8 -1 g10 -0 g10 -1 p27 b5 r1 g5 -0 g5 -1 g7 -0 g7 -1 g9 -0 g9 -1 p26 b4 r0 g4 -0 g4 -1 g6 -0 g6 -1 g8 -0 g8 -1 p25 b3 g7 g3 -0 g3 -1 g5 -0 g5 -1 g7 -0 g7 -1 p24 b2 g6 g2 -0 g2 -1 g4 -0 g4 -1 g6 -0 g6 -1 p23 b1 g5 g1 -0 g1 -1 g3 -0 g3 -1 g5 -0 g5 -1 p22 b0 g4 g0 -0 g0 -1 g2 -0 g2 -1 g4 -0 g4 -1 p21 z z z z g1 -0 g1 -1 g3 -0 g3 -1 p20 z z z z g0 -0 g0 -1 g2 -0 g2 -1 p19 g3 r7 b7 -0 b7 -1 b9 -0 b9 -1 b11 -0 b11 -1 p18 g2 r6 b6 -0 b6 -1 b8 -0 b8 -1 b10 -0 b10 -1 p17 g1 r5 b5 -0 b5 -1 b7 -0 b7 -1 b9 -0 b9 -1 p16 g0 r4 b4 -0 b4 -1 b6 -0 b6 -1 b8 -0 b8 -1 p15 z z b3 -0 b3 -1 b5 -0 b5 -1 b7 -0 b7 -1 p14 z z b2 -0 b2 -1 b4 -0 b4 -1 b6 -0 b6 -1 p13 z z b1 -0 b1 -1 b3 -0 b3 -1 b5 -0 b5 -1 p12 z z b0 -0 b0 -1 b2 -0 b2 -1 b4 -0 b4 -1 p11 z z z z b1 -0 b1 -1 b3 -0 b3 -0 p10 z z z z b0 -0 b0 -1 b2 -0 b2 -1 p9 z z r7 -0 r7 -1 r9 -0 r9 -1 r11 -0 r11 -1 p8 z z r6 -0 r6 -1 r8 -0 r8 -1 r10 -0 r10 -1 p7 z z r5 -0 r5 -1 r7 -0 r7 -1 r9 -0 r9 -1 p6 z z r4 -0 r4 -1 r6 -0 r6 -1 r8 -0 r8 -1 p5 z z r3 -0 r3 -1 r5 -0 r5 -1 r7 -0 r7 -1 p4 z z r2 -0 r2 -1 r4 -0 r4-1 r6 -0 r6 -1 p3 z z r1 -0 r1 -1 r3 -0 r3 -1 r5 -0 r5 -1 p2 z z r0 -0 r0 -1 r2 -0 r2 -1 r4 -0 r4 -1 p1 z z z z r1 -0 r1 -1 r3 -0 r3 -1 p0 z z z z r0 -0 r0 -1 r2 -0 r2 -1
data sheet ADV7802 re v. d | page 31 of 36 op_format_sel [5:0] 0x1d 0x38 0x39 0x3a pixel output 36- bit ddr rgb (clk/2) mode 2 16- bit and 8 - bit ddr 4:2:2 mode 1 parallel output (clk/2) 20- bit and 10 - bit ddr 4:2:2 mode 1 parallel output (clk /2) 24- bit and 12 - bit ddr 4:2:2 mode 1 parallel output (clk/2) clock rise clock fall clock rise clock fall clock rise clock fall clock rise clock fall p53 g 3 - 0 g3 - 1 main y1 main y1 p52 g2 - 0 g2 - 1 main y0 main y0 p51 g1 -0 g1 -1 z z p50 g0 -0 g0 -1 z z p49 z z z z p48 z z z z p47 z z z z p46 z z z z p45 b3 -0 b3 -1 main cb1 main cr1 p44 b2 -0 b2 -1 main cb0 main cr0 p43 b1 -0 b1 -1 z z p42 b0 -0 b0 -1 z z p41 z z z z p40 z z z z p39 z z z z p38 z z z z p37 r3 -0 r3 -1 aux cb 1 , cr1 aux cr0 p36 r2 -0 r2 -1 aux cb0, cr0 aux cr0 p35 r1 -0 r1 -1 z z p34 r0 - 0 r0 - 1 z z p33 z z z z p3 2 z z z z p31 z z z z p30 z z z z p29 g11 -0 g11 -1 main y7 main y7 main y9 main y9 main y11 main y11 p28 g10 -0 g10 -1 main y6 main y6 main y8 main y8 main y10 main y10 p27 g9 -0 g9 -1 main y5 main y5 main y7 main y7 main y9 main y9 p26 g8 -0 g8-1 main y4 main y4 main y6 main y6 main y8 main y8 p25 g7 -0 g7 -1 main y3 main y3 main y5 main y5 main y7 main y7 p24 g6 -0 g6 -1 main y2 main y2 main y4 main y4 main y6 main y6 p23 g5 - 0 g5 - 1 main y1 main y1 main y3 main y3 main y5 main y5 p22 g4 - 0 g4 - 1 main y0 main y0 main y2 main y2 main y4 main y4 p21 z z z z main y1 main y1 main y3 main y3 p20 z z z z main y0 main y0 main y2 main y2 p19 b11 -0 b11 -1 main cb7 main cr7 main cb9 main cr9 main cb11 main cr11 p18 b10 -0 b10 -1 main cb6 main cr6 main cb8 m ain cr8 main cb10 main cr10 p17 b9 -0 b9 -1 main cb5 main cr5 main cb7 main cr7 main cb9 main cr9 p16 b8 -0 b8 -1 main cb4 main cr4 main cb6 main cr6 main cb8 main cr8 p15 b7 -0 b7 -1 main cb3 main cr3 main cb5 main cr5 main cb7 main cr7 p14 b6 -0 b6 -1 main c b2 main cr2 main cb4 main cr4 main cb6 main cr6 p13 b5 -0 b5 -1 main cb1 main cr1 main cb3 main cr3 main cb5 main cr5 p12 b4 -0 b4 -1 main cb0 main cr0 main cb2 main cr2 main cb4 main cr4 p11 z z z z main cb1 main cr1 main cb3 main cr3 p10 z z z z main cb0 main cr0 main cb2 main cr2 p9 r11 -0 r11 -1 aux cb7, cr7 aux y7 aux cb9, cr9 aux y9 aux cb11, cr11 aux y11 p8 r10 -0 r10 -1 aux cb6, cr6 aux y6 aux cb8, cr8 aux y8 aux cb10, cr10 aux y10 p7 r9 -0 r9 -1 aux cb5, cr5 aux y5 aux cb7, cr7 aux y7 aux cb9, cr9 aux y9 p6 r8 -0 r8 -1 aux cb4, cr4 aux y4 aux cb6, cr6 aux y6 aux cb8, cr8 aux y8 p5 r7 -0 r7 -1 aux cb3, cr3 aux y3 aux cb5, cr5 aux y5 aux cb7, cr7 aux y7 p4 r6 -0 r6 -1 aux cb2, cr2 aux y2 aux cb4, cr4 aux y4 aux cb6, cr6 aux y6 p3 r5 -0 r5 -1 aux cb1, cr1 aux y1 aux cb3, cr3 aux y3 aux cb5, cr5 aux y5 p2 r4 -0 r4 -1 aux cb0, cr0 aux y0 aux cb2, cr2 aux y2 aux cb4, cr4 aux y4 p1 z z z z aux cb1, cr1 aux y1 aux cb3, cr3 aux y3 p0 z z z z aux cb0, cr0 aux y0 aux cb2, cr2 aux y2
ADV7802 data sheet rev. d | page 32 of 36 op_format_sel [5:0] 0x3b 0x3c 0 x3d 0x3e pixel output 24- bit and 12 - bit ddr 4:2:2 mode 2 parallel output (clk/2) 24- bit ddr 4:2:2 rgb (clk/2) 24- bit ddr 4:2:2 rgb ( clk/2) mode 1 24- bit ddr 4:2:2 rgb ( clk/2) mode 2 clock rise clock fall clock rise clock fall clock rise clock fall cloc k rise clock fall p53 main y3 main y3 p52 main y2 main y2 p51 main y1 main y1 p50 main y0 main y0 p49 z z p48 z z p47 z z p46 z z p45 main cb3 main cr3 p44 main cb2 main cr2 p43 main cb 1 main cr1 p42 main cb0 main cr0 p41 z z p40 z z p39 z z p38 z z p37 aux cb3, cr3 aux y3 p36 aux cb2, cr2 aux y2 p35 aux cb1, cr1 aux y1 p34 aux cb0, cr0 aux y0 p33 z z p32 z z p31 z z p30 z z p29 main y11 main y11 g7 -0 g7 -1 r7 -0 r7 -1 b7 -0 b7 -1 p28 main y10 main y10 g6 -0 g6 -1 r6 -0 r6 -1 b6 -0 b6 -1 p27 main y9 main y9 g5 -0 g5 -1 r5 -0 r5 -1 b5 -0 b5 -1 p26 main y8 main y8 g4 -0 g4 -1 r4 -0 r4 -1 b4 -0 b4 -1 p25 main y7 m ain y7 g3 -0 g3 -1 r3 -0 r3 -1 b3 -0 b3 -1 p24 main y6 main y6 g2 - 0 g2 - 1 r2 - 0 r2 - 1 b2 - 0 b2 - 1 p23 main y5 main y5 g1 - 0 g1 - 1 r1 - 0 r1 - 1 b1 - 0 b1 - 1 p22 main y4 main y4 g0 - 0 g0 - 1 r0 - 0 r0 - 1 b0 - 0 b0 - 1 p21 z z b7 -0 b7 -1 g7 -0 g7 -1 r7 -0 r7 -1 p20 z z b6 -0 b6 -1 g6 -0 g6 -1 r6 -0 r6 -1 p19 main cb11 main cr11 b5 -0 b5 -1 g5 -0 g5 -1 r5 -0 r5 -1 p18 main cb10 main cr10 b4 -0 b4 -1 g4 -0 g4 -1 r4 -0 r4 -1 p17 main cb9 main cr9 b3 -0 b3 -1 g3 -0 g3 -1 r3 -0 r3 -1 p16 main cb8 main cr8 b2 -0 b2 -1 g2 -0 g2 -1 r2 -0 r2 -1 p15 main cb7 main cr7 b1 -0 b1 -1 g1 -0 g1 -1 r1 -0 r1 -1 p14 main cb6 main cr6 b0 -0 b0 -1 g0 -0 g0 -1 r7 -0 r7 -1 p13 main cb5 main cr5 r7 -0 r7 -1 b7 -0 b7 -1 g7 -0 g7 -1 p12 main cb4 main cr4 r6 -0 r6 -1 b6 -0 b6 -1 g6 -0 g6 -1 p11 z z r5 -0 r5 -1 b5 -0 b5 -1 g5 -0 g5 -1 p10 z z r4 -0 r4 -1 b4 -0 b4 -1 g4 -0 g4 -1 p9 aux cb11, cr11 aux y11 r3 -0 r3 -1 b3 -0 b3 -1 g3 -0 g3 -1 p8 aux cb10, cr10 aux y10 r2 -0 r2 -1 b2 -0 b2 -1 g2 -0 g2 -1 p7 aux cb9, cr9 aux y9 r1 -0 r1 -1 b1 -0 b1 -1 g1 -0 g1 -1 p6 aux cb8, cr8 aux y8 r0 -0 r0 -1 b0 -0 b0 -1 g0 -0 g0 -1 p5 aux cb7, cr7 aux y7 z z z z z z p4 aux cb6, cr6 aux y6 z z z z z z p3 aux cb5, cr5 aux y5 z z z z z z p2 aux cb4, cr4 aux y4 z z z z z z p1 z z z z z z z z p0 z z z z z z z z
data sheet ADV7802 re v. d | page 33 of 36 table 10 . pixel port input modes ip_data_sel[5:0] 0x00 0x01 0x04 0x06 0x07 pixel input 24- bit 4:4:4 i nput 20- bit 4:2:2 input 16- bit 4:2:2 input 10- bit 4:2:2 input 8- bit 4:2:2 input p53 g7 y9 y7 y9, cb9, cr9 y7, cb7, cr7 p52 g6 y8 y6 y8, cb8, cr8 y6, cb6, cr6 p51 g5 y7 y5 y7, cb7, cr7 y5,cb5, cr5 p50 g4 y6 y4 y6, cb6, cr6 y4 , cb4, cr4 p49 g3 y5 y3 y5,cb5, cr5 y3, cb3, cr3 p48 g2 y4 y2 y4, cb4, cr4 y2, cb2, cr2 p47 g1 y3 y1 y3, cb3, cr3 y1, cb1, cr1 p46 g0 y2 y0 y2, cb2, cr2 y0, cb0, cr0 p45 b7 cb9, cr9 cb7, cr7 y1, cb1, cr1 z p44 b6 cb8, cr8 cb6, cr6 y0, cb0, cr0 z p43 b5 cb7, cr7 cb5, cr5 z z p42 b4 cb6, cr6 cb4, cr4 z z p41 b3 cb5, cr5 cb3, cr3 z z p40 b2 cb4, cr4 cb2, cr2 z z p39 b1 cb3, cr3 cb1, cr1 z z p38 b0 cb2, cr2 cb0, cr0 z z p37 r7 y1 z z z p36 r6 y0 z z z p35 r5 z z z z p34 r4 z z z z p33 r3 cb1, c r1 z z z p32 r2 cb0, cr0 z z z p31 r1 z z z z p3 0 r0 z z z z
ADV7802 data sheet rev. d | page 34 of 36 outline dimensions compliant t o jedec s t andards ms-026-bg a 051706- a top view (pins down) 133 1 132 45 44 88 89 176 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 26.20 26.00 sq 25.80 24.20 24.00 sq 23.80 figure 12 . 176 - lead low profile quad flat package [lqfp] (st - 176 ) dimensions shown in millimeters ordering guide model 1 temperature range pack age description package option ADV7802bstz -80 0c to +85c 176- lead low profile quad flat package [lqfp] st- 176 ADV7802b stz - 150 0c to +85c 176 - lead low profile quad flat package [lqfp] st - 176 eval - ADV7802eb 1z evaluation b oard (with external ddr sd me mory) 1 z = rohs compliant part.
data sheet ADV7802 re v. d | page 35 of 36 notes
ADV7802 data sheet rev. d | page 36 of 36 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06654 -0- 8/11(d)

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